Referring to FIG. 1 of the drawings the reference numeral 100 generally designates a conventional circuit. Circuit 100 has a driver 102 that receives a differential input signal through input terminals INP and INN to drive a load 104 (which includes a resistance RL). Also, driver 102 generally comprises NPN transistors Q1 and Q2, NMOS transistors Q3 and Q4, resistors R1 and R2, and current source 106.
In operation, driver 102 provides currents through output terminals OUTP and OUTN to drive the load 104. When a logic high or “1” is applied to the base of transistor Q1 and a logic low or “0” is applied to the base of transistor Q2, current is sourced through transistor Q1 and resistor R1 to terminal OUTP, while transistor Q4 (because transistors Q3 and Q4 are cross-coupled) sinks current from output terminal OUTN. Alternatively, when a logic high or “1” is applied to the base of transistor Q2 and a logic low or “0” is applied to the base of transistor Q1, current is sourced through transistor Q2 and resistor R2 to terminal OUTN, while transistor Q3 (again because transistors Q3 and Q4 are cross-coupled) sinks current from output terminal OUTP.
With this configuration, though, the switching speeds of transistors Q3 and Q4 are limiting factors for the operational speed of the driver 102. In bipolar CMOS or BiCMOS processes, transistors (which are field effect transistors or FETs) have low switching speeds, so driver 102 is undesirable for integrated circuits or ICs manufactured using BiCMOS processes. Simply replacing transistors Q3 and Q4 with bipolar transistors (i.e., NPN transistors), though, to take advantage of higher switching speeds would also be undesirable because the junction diodes of the bipolar transistors would limit the output voltage swings. Additionally, because of the properties of transistors Q3 and Q4, electrostatic discharge or ESD events across terminals OUTP and OUTN may damage transistors Q3 and Q4. Moreover, use of transistors Q3 and Q4 may result in ringing and/or latch-up from positive feedback. Therefore, there is a need for an improved driver.
Some other conventional circuits are: U.S. Pat. No. 6,847,232; U.S. Patent Pre-Grant Publ. No. 2002/0140461; European Patent no. EP0476341; and Abugharbieh et al., “An ultra low power 10 Gbps LVDS output driver”, Bipolar/BiCMOS Circuits and Technology Meeting, 2008, Oct. 13-15, 2008, Pgs. 5-8.